The physical synthesis of a circuit design refers to the process of transforming a gate-level representation of the circuit design into a physical implementation of the circuit design (i.e. a chip layout). Due to the complexity of circuit designs, electronic design automation (EDA) tools are used to perform the physical synthesis. During physical synthesis, components or technology-specific logic gates of the circuit design are assigned to specific locations within a prescribed chip area of the circuit design. Interconnects between the components, referred to as nets, are then wire routed to provide signal connectivity between the components. One of the goals of physical synthesis is to achieve design closure. That is, to create a physical implementation of the circuit design that meets the design's performance, power, signal integrity, and timing objectives.
As technology scaling has caused wire delays to increase relative to gate delays, design closure is becoming more difficult because wire delays introduced during the routing of the circuit design are becoming a significant source of timing violations. As a result, the physical synthesis of a circuit design may take many iterations of optimizing the placement and routing of the circuit design before the timing requirements are met. For complex circuit designs, this may take days to weeks before design closure is achieved. To improve time it takes to reach timing closure, electronic design automation (EDA) tools use wire delay estimates of nets in the circuit design to assist with placement and routing decisions. However, average resistance and capacitance (RC) values are used for calculating these delay estimates. This often leads to inaccurate wire delay estimates resulting in little improvement in the overall time it takes to reach design closure.